:experimental:

[[inspecting-a-schematic]]
== Inspecting a schematic

=== Find tool

The Find tool searches for text in the schematic, including reference
designators, pin names, symbol fields, and graphic text. When the tool finds a
match, the canvas is zoomed and centered on the match and the text is
highlighted. Launch the tool using the image:images/icons/find_24.png[Find icon]
button in the top toolbar.

image::images/en/find_dialog.png[alt="Find dialog",scaledwidth="50%"]

The Find tool has several options:

*Match case:* Selects whether the search is case-sensitive.

*Words:* When selected, the search will only match the search term with complete
words in the schematic. When unselected, the search will match if the search
term is part of a larger word in the schematic.

*Wildcards:* When selected, wildcards can be used in the search terms. `?`
matches any single character, and `\*` matches any number of characters. Note
that when this option is selected, partial matches are not returned: searching
for `abc*` will match the string `abcd`, but searching for `abc` will not.

*Search pin names and numbers:* Selects whether the search should apply to pin
names and numbers.

*Search hidden fields:* Selects whether the search should apply only to visible
fields or if it should include hidden symbol fields.

*Search the current sheet only:* Selects whether the search should be limited to
the current schematic sheet or to the entire schematic.

There is also a Find and Replace tool which is activated with the
image:images/icons/find_replace_24.png[Find and Replace icon] button in the top
toolbar. This tool behaves the same as the Find tool, but additionally can
replace some or all matches with different text.

image::images/en/find_replace_dialog.png[alt="Find and Replace dialog",scaledwidth="50%"]

If the *Replace matches in reference designators* option is checked, reference
designators will be modified if they contain matching text. Otherwise reference
designators will not be affected.

=== Net highlighting

An electrical net can be highlighted in the schematic editor to visualize all of
the places it appears in the schematic. Net highlighting can be activated in the
Schematic Editor or by highlighting the corresponding net in the PCB editor when
cross-probe highlighting is enabled (see below). When net highlighting is
active, the highlighted net will be shown in a different color. By default this
color is pink, but it is configurable in the Color section of the Preferences
dialog.

Nets can be highlighted by clicking on a wire or pin using the Highlight Net
tool in the right toolbar (image:images/icons/net_highlight_schematic_24.png[Net
Highlight icon]). Alternatively, the Highlight Net hotkey (kbd:[`]) highlights
the net under the cursor. If there are no nets or pins under the cursor, any
existing highlighting will be cleared. The highlighting can also be cleared by
using the Clear Net Highlight action (hotkey kbd:[~]).

=== Cross-probing from the PCB

KiCad allows bi-directional cross-probing between the schematic and the PCB.
There are several different types of cross-probing.

*Selection cross-probing* allows you to select a symbol or pin in the schematic
to select the corresponding footprint or pad in the PCB (if one exists) and
vice-versa. By default, cross-probing will result in the display centering on
the cross-probed item and zooming to fit. This behavior can be disabled in the
Display Options section of the Preferences dialog.

*Highlight cross-probing* allows you to highlight a net in the schematic and PCB
at the same time. If the option "Highlight cross-probed nets" is enabled in the
Display Options section of the Preferences dialog, highlighting a net or bus in
the schematic editor will cause the corresponding net or nets to be highlighted
in the PCB editor, and vice versa.


[[erc]]
=== Design verification with Electrical Rules Check

The Electrical Rules Check (ERC) tool performs an automatic check of your
schematic. The ERC checks for any errors in your sheet, such as unconnected
pins, unconnected hierarchical symbols, shorted outputs, etc. ERC output is
reported as errors or warnings depending on the severity of the issue detected.

Naturally, an automatic check is not infallible, and it is not possible to
detect all design errors.  Such a check is still very useful, because it allows
you to detect many oversights and small errors. All detected issues should be
checked and addressed before proceeding.

The quality of the ERC is directly related to the care taken in declaring
<<pin-electrical-types,electrical pin properties>> during symbol library
creation.

ERC can be started by clicking on the
image:images/icons/erc_24.png[ERC icon] button in the top toolbar and clicking
the **Run ERC** button.

image::images/en/dialog_erc.png[alt="ERC dialog",scaledwidth="70%"]

Any warnings or errors are reported in the **Violations** tab, and markers for
each violation are placed in the schematic so that they point to the relevant
part of the schematic. Warnings are indicated by yellow arrows, and errors have
red arrows. Excluded violations are shown as green arrows.

NOTE: Selecting a violation in the ERC window jumps to the selected violation marker
in the schematic.

The numbers at the bottom of the window show the number of errors, warnings, and
exclusions. Each type of violation can be filtered from the list using the
respective checkboxes. Clicking **Delete Markers** will clear all violations
until ERC is run again.

Violations can be right-clicked in the dialog to ignore them or change their severity:

image::images/erc_ignore_warning.png[alt="Ignore ERC warning",scaledwidth="70%"]

* *Exclude this violation:* ignores this particular violation, but does not
  affect any other violations.
* *Change severity:* changes a type of violation from warning to error, or error
  to warning. This affects all violations of a given type.
* *Ignore all:* ignores all violations of a given type.

==== ERC example

image::images/erc_pointers.png[alt="ERC pointers",scaledwidth="70%"]

Here you can see three errors:

* Two outputs have been connected together (red arrow at right).
* Two inputs have been left unconnected (red arrows at left).

Selecting an ERC marker displays a description of the violation in the message
pane at the bottom of the window.

image::images/erc_pointers_message.png[alt="ERC violation description in message pane",scaledwidth="80%"]

[[power-pins-and-power-flags]]
==== Power pins and power flags

It is common to have an "Input Power pin not driven by any Output Power pins"
error on power pins, as shown in the example below, even though the power pins
seem to be properly connected to a power rail. This happens in designs where the
power is provided through connectors or other components that are not marked as
power outputs. In these cases ERC won't detect any Output Power pins connected
to the net and will determine the Input Power pin is not driven by a power
source.

image::images/eeschema_power_pins_and_flags.png[alt="Power pins and error flags",scaledwidth="70%"]

To avoid this warning, connect the net to `PWR_FLAG` symbol on such a power net
as shown in the following example. The `PWR_FLAG` symbol is found in the `power`
symbol library. Alternatively, connect any power output pin to the net;
`PWR_FLAG` is simply a symbol with a single power output pin.

image::images/eeschema_power_pins_and_flags.png[alt="Power pins with PWR_FLAGs",scaledwidth="70%"]

Ground nets often need a `PWR_FLAG` as well, because voltage regulators have
outputs declared as power outputs, but their ground pins are typically marked as
power inputs. Therefore grounds can appear unconnected to a source unless a
`PWR_FLAG` symbol is used.

For more information about power pins and power flags, see the
<<pwr-flag,`PWR_FLAG` documentation>>.

[[erc-configuration]]
==== ERC Configuration

The _Pin Conflicts Map_ panel in <<schematic-setup,Schematic Setup>> allows you
to configure connectivity rules to define electrical conditions for errors and
warnings based on what types of pins are connected to each other.

image::images/eeschema_erc_options.png[alt="Schematic ERC Pin Conflicts Map",scaledwidth="70%"]

Rules can be changed by clicking on the desired square of the matrix,
causing it to cycle through the choices: normal, warning, error.

image::images/eeschema_erc_severity.png[alt="Schematic ERC severity settings",scaledwidth="70%"]

The _Violation Severity_ panel in <<schematic-setup,Schematic Setup>> lets you
configure what types of ERC messages should be reported as Errors, Warnings or
ignored.

[[erc-report-file]]
==== ERC report file

An ERC report file can be generated and saved by clicking the **Save...** button
in the ERC dialog. The file extension for ERC report files is `.rpt`. Here is an
example ERC report file.

----------------------------------------------------------------------
ERC report (Fri 21 Oct 2022 02:07:05 PM EDT, Encoding UTF8)

***** Sheet /
[pin_not_driven]: Input pin not driven by any Output pins
    ; Severity: error
    @(149.86 mm, 60.96 mm): Symbol U1B [74LS00] Pin 4 [, Input, Line]
[pin_not_connected]: Pin not connected
    ; Severity: error
    @(149.86 mm, 60.96 mm): Symbol U1B [74LS00] Pin 4 [, Input, Line]
[pin_not_connected]: Pin not connected
    ; Severity: error
    @(149.86 mm, 66.04 mm): Symbol U1B [74LS00] Pin 5 [, Input, Line]
[pin_to_pin]: Pins of type Output and Output are connected
    ; Severity: error
    @(165.10 mm, 63.50 mm): Symbol U1B [74LS00] Pin 6 [, Output, Inverted]
    @(165.10 mm, 46.99 mm): Symbol U1A [74LS00] Pin 3 [, Output, Inverted]
[pin_not_driven]: Input pin not driven by any Output pins
    ; Severity: error
    @(149.86 mm, 66.04 mm): Symbol U1B [74LS00] Pin 5 [, Input, Line]

 ** ERC messages: 5  Errors 5  Warnings 0
----------------------------------------------------------------------
